Lehrinhalte
The module deals with synthesis steps on all abstraction layers below the register transfer level focusing on approaches suitable for FPGAs. At the logic level different types of minimization are explained (exact and heuristic two level minimizations, exact and heuristic multi level logic minimizations). The transition to the technology level is achieved by different decomposition and structural mapping techniques (FlowMap). Place&Route add geometric information to the technology mapped circuit. Analytical and heuristic placers are discussed (Simulated Annealing, Genetic Placers) and routing is illustrated through the PathFinder algorithm.
Literatur
A script of the lecture (in German) and English foils can be obtained from here: [url]http://www.rs.tu-darmstadt.de/[/url]
Voraussetzungen
Knowledge of hardware synthesis on the basis of at least one hardware description language is required (e.g. Reese/Thornton: Introduction to Logic Synthesis Using Verilog Hdl oder Brown/Vranesic: Fundamentals of Digital Logic with VHDL Design). The student should have basic knowledge of at least one object oriented programming language, preferably Java
Further Grading Information
Attention:
Due to a sabbatical in summer semester 2019, Prof. Hochberger will not hold the weekly lectures. Instead, we offer the recordings from last year
slides for self study. The exercises will be supervised by Dennis Wolf
in the usual way. In the first week of the semester there will be an administrative meeting to answer all upcoming questions.
In summer semester 2020 the lecture will again be offered in the usual form.
Stammraum Informationen
S306/053
Additional Information
[url]http://www.rs.tu-darmstadt.de[/url]
The module deals with synthesis steps on all abstraction layers below the register transfer level focusing on approaches suitable for FPGAs. At the logic level different types of minimization are explained (exact and heuristic two level minimizations, exact and heuristic multi level logic minimizations). The transition to the technology level is achieved by different decomposition and structural mapping techniques (FlowMap). Place&Route add geometric information to the technology mapped circuit. Analytical and heuristic placers are discussed (Simulated Annealing, Genetic Placers) and routing is illustrated through the PathFinder algorithm.
Literatur
A script of the lecture (in German) and English foils can be obtained from here: [url]http://www.rs.tu-darmstadt.de/[/url]
Voraussetzungen
Knowledge of hardware synthesis on the basis of at least one hardware description language is required (e.g. Reese/Thornton: Introduction to Logic Synthesis Using Verilog Hdl oder Brown/Vranesic: Fundamentals of Digital Logic with VHDL Design). The student should have basic knowledge of at least one object oriented programming language, preferably Java
Further Grading Information
Attention:
Due to a sabbatical in summer semester 2019, Prof. Hochberger will not hold the weekly lectures. Instead, we offer the recordings from last year
slides for self study. The exercises will be supervised by Dennis Wolf
in the usual way. In the first week of the semester there will be an administrative meeting to answer all upcoming questions.
In summer semester 2020 the lecture will again be offered in the usual form.
Stammraum Informationen
S306/053
Additional Information
[url]http://www.rs.tu-darmstadt.de[/url]
- Lehrende: HochbergerChristian
Semester: ST 2019