Lehrinhalte
[list]
[*]Mapping of behavioral descriptions (e.g. in the form of program fragments) on FPGA and CGRA structures
[*]Sub-tasks allocation, scheduling, binding
[*]Exact or heuristic solutions
[*]Design principles of heuristic solutions
[/list]
Literatur
English slides can be obtained through Moodle.
Voraussetzungen
Knowledge of hardware synthesis on the basis of at least one hardware description lan-guage is required (e.g. Reese/Thornton: Introduction to Logic Synthesis Using Verilog Hdl oder Brown/Vranesic: Fundamentals of Digital Logic with VHDL Design). The student should have basic knowledge of at least one object oriented programming lan-guage, preferably Java
Online-Angebote
moodle
[list]
[*]Mapping of behavioral descriptions (e.g. in the form of program fragments) on FPGA and CGRA structures
[*]Sub-tasks allocation, scheduling, binding
[*]Exact or heuristic solutions
[*]Design principles of heuristic solutions
[/list]
Literatur
English slides can be obtained through Moodle.
Voraussetzungen
Knowledge of hardware synthesis on the basis of at least one hardware description lan-guage is required (e.g. Reese/Thornton: Introduction to Logic Synthesis Using Verilog Hdl oder Brown/Vranesic: Fundamentals of Digital Logic with VHDL Design). The student should have basic knowledge of at least one object oriented programming lan-guage, preferably Java
Online-Angebote
moodle
- Lehrende: Christian Hochberger
Semester: WT 2020/21