Course Contents
Realisation of a VHDL- or Verilog-based VLSI System Design Project in a Team with industrial constraints
Literature
Lecture slides CAD4SoC"
Preconditions
Mandatory Prerequisite: Lecture Computer Aided Design for SoCs,
At least one high-level Programming Language, Basic Know-How Linux/Unix, Computer Architectures
Realisation of a VHDL- or Verilog-based VLSI System Design Project in a Team with industrial constraints
Literature
Lecture slides CAD4SoC"
Preconditions
Mandatory Prerequisite: Lecture Computer Aided Design for SoCs,
At least one high-level Programming Language, Basic Know-How Linux/Unix, Computer Architectures
- Lehrende: Klaus Hofmann
- Lehrende: Dominic Korner
Semester: Verão 2022