Lehrinhalte
The module deals with synthesis steps on all abstraction layers below the register transfer level focusing on approaches suitable for FPGAs. At the logic level different types of minimization are explained (exact and heuristic two level minimizations, exact and heuristic multi level logic minimizations). The transition to the technology level is achieved by different decomposition and structural mapping techniques (FlowMap). Place&Route add geometric information to the technology mapped circuit. Analytical and heuristic placers are discussed (Simulated Annealing, Genetic Placers) and routing is illustrated through the PathFinder algorithm.
Literatur
A script of the lecture (in German) and English foils can be obtained from here: [url]http://www.rs.tu-darmstadt.de/[/url]
Voraussetzungen
Knowledge of hardware synthesis on the basis of at least one hardware description language is required (e.g. Reese/Thornton: Introduction to Logic Synthesis Using Verilog Hdl oder Brown/Vranesic: Fundamentals of Digital Logic with VHDL Design). The student should have basic knowledge of at least one object oriented programming language, preferably Java
Additional Information
[url]http://www.rs.tu-darmstadt.de[/url]
The module deals with synthesis steps on all abstraction layers below the register transfer level focusing on approaches suitable for FPGAs. At the logic level different types of minimization are explained (exact and heuristic two level minimizations, exact and heuristic multi level logic minimizations). The transition to the technology level is achieved by different decomposition and structural mapping techniques (FlowMap). Place&Route add geometric information to the technology mapped circuit. Analytical and heuristic placers are discussed (Simulated Annealing, Genetic Placers) and routing is illustrated through the PathFinder algorithm.
Literatur
A script of the lecture (in German) and English foils can be obtained from here: [url]http://www.rs.tu-darmstadt.de/[/url]
Voraussetzungen
Knowledge of hardware synthesis on the basis of at least one hardware description language is required (e.g. Reese/Thornton: Introduction to Logic Synthesis Using Verilog Hdl oder Brown/Vranesic: Fundamentals of Digital Logic with VHDL Design). The student should have basic knowledge of at least one object oriented programming language, preferably Java
Additional Information
[url]http://www.rs.tu-darmstadt.de[/url]
- Lehrende: Christian Hochberger
Semester: ST 2020